What are the responsibilities and job description for the Senior Principal Architect position at Infineon Technologies AG?
As a Sr. Principal Architect, you will work with IP owners to clearly specify architectural and micro-architectural design parameters. Does this sound exciting? If so, please apply today!In your new role you will : Reporting to the VP / Fellow, Platform Architecture. This position is responsible for driving Platform and IP Architecture.Write System and IP Architecture Specifications for the MXS40Sv2 and MXS22 platforms.Guide product architects during feasibility, definition, and design phases.Work with IP owners to clearly specify architectural and micro-architectural design parameters.Work with product marketing and product architects to define platform enhancements that support product requirements.Identify and lead continuous improvements in platform development processes.Work with boot, firmware, and software teams to ensure software compatibility and migration plans.Work closely with IP owners to understand design impact of architectural changes.Support product architects in understanding platform capabilities, parametrizable features, configurable options, and platform performance.Minimum requirements : BSEE, MSEE (preferred).20 years of experience leading a platform architecture team used in multiple products in production : SoC architecture, IP architecture, and systems engineering (hardware / software partitioning) for multiple market segments.Strong understanding of Cortex-M M0, M33, and M55 32-bit processors; interfaces / protocols (eg AMBA AXI, AHB, APB, etc); power management interfaces / protocols (eg LPI, PPU, etc); security (eg RoT, TrustZone, PSA L2 / L3 / L4, protection context, CIA, threat modeling, etc); and performance estimation.Excellent technical writing skills, because much of the job is writing hardware specifications that are forward looking.Proven track record leading cross-functional teams, while driving system, hardware, firmware, and software tradeoffs.Positive approach to challenging assignments.Additional experience (a plus) : Experience writing machine-readable executable specifications.Hands on experience developing solutions with heterogeneous multi-processors and efficient inter-processor communication in the same package / die.Firm understanding of process isolation (including hardware accelerators).Hands-on experience with real-time embedded operating systems : especially bare metal assembly / C programming, debug, trace, interrupt service routines, exception handling, cache management, memory management, memory protection, virtual-to-physical address translation, TLB, inter-processor communication, concurrent programming, etc.Strong understanding of Cortex-M M85 and embedded RISC-V processors.#J-18808-Ljbffr