Design Engineer

Job Title: ASIC/RTL Design Engineer

Primary Skills : RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime).

Location: Santa Clara, CA

Duration : 12 Months

Job Description:

Location: San Jose - Onsite

Interviews: Interviews will be online. Two interviews.

Top skills:

RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime).

JOB DUTIES:

The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and AMD internal IP's. Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes.

Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.

EXPERIENCE AND EDUCATION:

- SoC Design;

- Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification, and supporting synthesis and timing closure.

- Experience with front end quality checks such as Lint, CDC, RDC. Running, Debugging, Reporting, Driving Cleanup.

- Working knowledge of ARM cores and other I/O standard interfaces.

- Roughly 10 years experience, but less is acceptable.

- Bachelors in electrical engineering or computer engineering is preferred

An ideal candidate would also exhibit: Strong communication and documentation skills, Good organizational, time management and multitasking skills, Strong initiative and discipline to follow-through, Technical leadership

Thanks & Regards

Shaik Sadeq

Infobahn Soft world Inc.

Email: Sadeq@infobahnsw.com