What are the responsibilities and job description for the Senior ASIC Engineer, Static Timing Analysis at Longmont, Colorado position at Infobahn Softworld Inc.?
Job Details
Role Title: Senior ASIC Engineer, Static Timing Analysis
Location: Longmont, CO - Onsite/Hybrid (3x per week)
Duration: 12 months contract
PREFERRED EXPERIENCE:
- Minimum of 6-8 years' experience
- Worked with EDA tools that enable RTL quality checks
- Experience with analyzing the timing reports and identifying both the design and constraints related issues.
- Ability to multitask, ramp up quickly on new flows/tools/ideas
- Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. - other EDA tool experience acceptable
DESCRIPTION:
- Understand the PT/DC checks and review the reports to help clean up in order to meet each milestone targets
- Summarize the regression results periodically to track the progress.
- Able to debug the basic issues like SDC loading errors, check_timing (no_clock, unconstrained, no_clock, QoR violations)
- Attention to the detail
- Very good communication skills (both written and verbal)
- Fast learner and self-starter. Need to execute our custom regression scripts/quality checks for our complex designs (Multimode, multimillion gates and multiple partitions)
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