What are the responsibilities and job description for the Senior Design Verification Engineer (ASIC/RTL) position at Infobahn Softworld Inc?
PREFERRED EXPERIENCE:
- Experience with C/C
- Experience with Verilog, System Verilog, and modern verification libraries like UVM
- 10 years of ASIC design verification experience
- Experience / Background with DDR or Memory Controller. PHY Verification is a plus
- Experience with scripting languages like Python, Perl and TCL is a plus.
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
- Understanding of Design for Test methodologies and DFT verification experience is a plus
- Proficient in debugging firmware and RTL code using simulation tools
KEY RESPONSIBILITIES:
- Develop/Maintain tests for functional verification.
- Build the directed and random verification tests, debug test failures to determine the root cause, work with RTL and firmware engineers to resolve design defects and correct any test issues.
- Work on functional & code coverage verification.
- Provide technical support to other teams
