What are the responsibilities and job description for the FE Process Integration Engineer position at Intel Corporation?
Job Details
Job Description:
Fab Sort Manufacturing (FSM) is responsible for producing all Intel silicon using advanced manufacturing processes.
In alignment with Intel's IDM2.0 strategy, FSM is expanding operations to meet the demands of both internal and foundry customers, introducing state-of-the-art technologies into high-volume manufacturing.
Intel has established the HVM Global Yield organization within FSM to enhance yield operations and facilitate rapid yield ramp-up during early high-volume manufacturing phases, collaborating with the Technology Development team and FSM Fab managers.
This job requisition seeks Front-End-Of-Line (FEOL) Process Integration engineers for the HVM Global Yield organization, reporting to the FEOL Process Integration manager.
Selected candidates will collaborate with FEOL integration members, Global Yield teams, fab modules, and TD team members to optimize processes and achieve yield ramp-up in the early production stage, supporting both internal and external customers.
FEOL (Front-End-Of-Line) Integration Development Engineers Are Responsible For
Minimum Qualifications:
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location:
US, Arizona, Phoenix
Additional Locations:
Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://jobs.intel.com/en/benefits
Annual Salary Range for jobs which could be performed in the US:
$130,300.00-$183,950.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
Job Description:
Fab Sort Manufacturing (FSM) is responsible for producing all Intel silicon using advanced manufacturing processes.
In alignment with Intel's IDM2.0 strategy, FSM is expanding operations to meet the demands of both internal and foundry customers, introducing state-of-the-art technologies into high-volume manufacturing.
Intel has established the HVM Global Yield organization within FSM to enhance yield operations and facilitate rapid yield ramp-up during early high-volume manufacturing phases, collaborating with the Technology Development team and FSM Fab managers.
This job requisition seeks Front-End-Of-Line (FEOL) Process Integration engineers for the HVM Global Yield organization, reporting to the FEOL Process Integration manager.
Selected candidates will collaborate with FEOL integration members, Global Yield teams, fab modules, and TD team members to optimize processes and achieve yield ramp-up in the early production stage, supporting both internal and external customers.
FEOL (Front-End-Of-Line) Integration Development Engineers Are Responsible For
- Leading engineering projects to execute high-volume manufacturing (HVM) yield roadmaps and achieve performance targets.
- Collaborating with Technology Development and Local Yield teams to implement new technologies in production fabs.
- Working with FEOL/BEOL Integration, Device, Defect Reduction, and Yield Analysis teams to identify root causes of yield and performance issues and executing mitigation plans within set timelines.
- Conducting feasibility studies and experiments to characterize processes and enhance product performance throughout development.
- Managing New Product Introductions (NPI) in production fabs and optimizing processes to meet foundry customer specifications.
- Partnering with Local Yield teams to improve product yield, quality, performance, and reduce wafer costs.
Minimum Qualifications:
- Bachelor's degree in a relevant science or engineering field, with at least 3 years of semiconductor industry experience.
- Experience in advanced node semiconductor industry, specifically in FEOL Process Integration
- Proficient understanding of Device Physics, with experience in FinFET or Gate-All-Around technology development or high-volume manufacturing.
- Familiarity with module processes such as lithography, dry etch, wet etch, CMP, diffusion, implant, thin films, and metrology.
- Level of experience will be considered in determining applicants job grade.
- Advanced degree (Master's or Ph.D.) in Electrical Engineering, Physics, or Materials Science; related fields may be considered based on industry experience.
- Experience in project/program management and/or as a TFT lead.
- Strong interpersonal skills, including the ability to influence and motivate others.
- Experience engaging with external foundry customers through technical interactions.
- Familiarity with GAA (Gate-All-Around) technology architecture.
- Background in new semiconductor technology development.
- Strong problem-solving skills, self-initiative, and ability to learn independently.
- Ability to collaborate effectively with multi-functional and multi-cultural teams.
- Excellent communication skills.
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location:
US, Arizona, Phoenix
Additional Locations:
Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://jobs.intel.com/en/benefits
Annual Salary Range for jobs which could be performed in the US:
$130,300.00-$183,950.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
Salary : $130,300 - $183,950
