Mixed Signal Logic Design Engineer

Job Details

Job Description:

Do Something Wonderful!

Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and have a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

Intel's centralized hard IP design in Folsom California is looking for senior logic design engineers to work on the next generation state-of-the-art IP technology. Our group is responsible for designing next generation Hard IP for the use across Intel's SOC products.

Who You Are

Responsibilities include but are not limited to:

• Your duties will be applied within the entire scope of Front End and design development including micro architecture definition, writing system verilog RTL code per micro architecture spec, debugging failing tests, building simulation models, coding per power aware methodologies (UPF), and various FE tools and methodologies.
• Other responsibilities may include working with back-end designers in timing convergence and other silicon area optimization etc.
• Your work will directly contribute to the design and health of Intel architecture based next generation SOC products.
• Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
• Participates in the definition of architecture and microarchitecture features of the block being designed.
• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• Supports SoC customers to ensure high quality integration and verification of the IP block. Drives quality assurance compliance for smooth IPSoC handoff.
• Strong written and verbal communication skills
  
  

Qualifications

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• The candidate must have a bachelors or graduate degree in Electrical or Computer Engineering
• 3 years’ of experience in RTL logic design and micro architecture experience
• 3 years’ of experience in power management hardware and firmware design/support
• 2 years’ experience with test-benches, simulation, validation and modeling theory is a plus
• 2 years’ experience with C and perl programming skills are plus
  
  

Preferred Qualifications

• Knowledge and fundamentals in Logic design, computer architecture and VLSI design concepts
• Knowledge in system verilog language and other simulation tools like VCS
  
  

Job Type

College Grad

Shift

Shift 1 (United States of America)

Primary Location:

US, California, Folsom

Additional Locations:

US, California, Santa Clara, US, Colorado, Fort Collins, US, Oregon, Hillsboro

Business Group

The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$139,710.00-$197,230.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

The application window for this job posting is expected to end by 04/18/2026