What are the responsibilities and job description for the Physical Design, Power Delivery, or Analog Graduate Engineering Intern position at Intel Corporation?
Job Description
Do Something Wonderful!
Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.
Who We Are
Do you want to collaborate with the best minds in the world? Do you love the idea of directly impacting Intel's future CPU generations? Come intern with our team this summer.
In this graduate internship, you will be working alongside a World-class SOC design team within the Xeon Engineering Group (XEG) delivering on next-generation Xeon products for Server markets, with a focus on AI enabling SOCs.
Responsibilities may be quite diverse of a nonexempt technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school.
Who You Are
Your responsibilities will include but are not limited to:
You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
The candidate must be pursuing a Master’s or PhD in Electrical or Computer Engineering, or a related field.
Preferred Qualifications
6 months of experience/coursework with:
Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.
Other Locations
US, OR, Hillsboro; US, CA, Santa Clara
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
Annual Salary Range for jobs which could be performed in the US $63,000.00-$166,000.00
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
Do Something Wonderful!
Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.
Who We Are
Do you want to collaborate with the best minds in the world? Do you love the idea of directly impacting Intel's future CPU generations? Come intern with our team this summer.
In this graduate internship, you will be working alongside a World-class SOC design team within the Xeon Engineering Group (XEG) delivering on next-generation Xeon products for Server markets, with a focus on AI enabling SOCs.
Responsibilities may be quite diverse of a nonexempt technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school.
Who You Are
Your responsibilities will include but are not limited to:
- Logic synthesis of design blocks, Auto Place-and-Route (APR) using Synopsys ICC tools
- Timing verification using Synopsys Primetime, Formal Equivalence Verification (FEV)
- Design and analysis of power delivery network
- Develop and run models to measure AC noise and DC droop
- Integrate analog IPs into SOC
- Block-level floor planning
- Participate in the design and development of AI enabling SOCs
- Teamwork skills
- Strong electrical fundamental skills
- Strong analog circuit skills
- Knowledge of RLC circuits/networks
- Excellent communication skills
- Problem solving skills
- Willingness to work independently and at various levels of abstraction
- Availability to commit to an on-site or virtual co-op over school break during the summer months, minimum of 3 months.
You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
The candidate must be pursuing a Master’s or PhD in Electrical or Computer Engineering, or a related field.
Preferred Qualifications
6 months of experience/coursework with:
- CMOS transistor level circuit fundamentals
- VLSI hardware design and programming
- Analog circuit design
- Voltage regulator fundamentals
- Electronic Design Automation tools, flows and methodology
- ICCDP, Design Compiler, IC Compiler/ICC, Primetime, VCS, Verilog
- Spice or Hardware modeling skills
- Cadence or Synopsys modeling tools
- Circuit design
- TCL, Python, Perl and/or C programming
Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.
Other Locations
US, OR, Hillsboro; US, CA, Santa Clara
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
Annual Salary Range for jobs which could be performed in the US $63,000.00-$166,000.00
- Salary range dependent on a number of factors including location and experience
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
Salary : $63,000 - $166,000
