What are the responsibilities and job description for the Physical Verification QA/Development Engineer position at Intel Corporation?
Job Description
At Intel, Design Technology Platform (DTP) is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies. As part of the Design Technology Platform/Process Design Kit (PDK) group, you will join a highly motivated team of talented engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers.
Responsibilities
In the Runset QA domain and as a DRC/LVS Physical Verification and QA Engineer, your responsibilities will include, but are not limited to:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
Experience in the following:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
Other Locations
US, TX, Austin; US, AZ, Phoenix; US, CA, Folsom; US, CA, Santa Clara
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
Annual Salary Range for jobs which could be performed in the US $146,520.00-$206,860.00
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
At Intel, Design Technology Platform (DTP) is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies. As part of the Design Technology Platform/Process Design Kit (PDK) group, you will join a highly motivated team of talented engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers.
Responsibilities
In the Runset QA domain and as a DRC/LVS Physical Verification and QA Engineer, your responsibilities will include, but are not limited to:
- Develop test patterns to qualify design rules for correct implementations.
- Develop automation to run regressions, auto detect issues and generate validation reports.
- You are also expected to file bug reports and work closely with runset developers and rule writers on validating the rules.
- Work closely with Technology development on providing feedback on rule wording and correctness.
- Partner with rules owners to ensure clarity and accuracy of rules.
- Work with EDA on tool developments/improvements to enhance performance, add functionality and improve capacity.
- Capturing user stories/requirements, writing both functional and test code, automating build and deployment, and/or performing unit, integration, and end to end testing of the software tools.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
- Candidate must possess a BS degree with 3 years of experience or MS degree with 2 years of experience or PhD degree with 1 years of experience in electrical engineering, computer engineering, computer science or related fields.
- Experience in the following:
- Developing Calibre or ICV runsets and validation test cases.
- fluent in at least one of the following: TCL, Python, Unix-Linux platforms
- Algorithmic development and translating rules into runsets.
Experience in the following:
- Developing test cases to validate DRC, LVS, antenna, density, and fill modules.
- Calibre PERC, and Cadence Pegasus.
- Layout and/or schematic entry using Cadence Virtuoso and/or Synopsys Custom Designer.
- Semiconductor device physics models and technology scaling.
- Algorithmic development and translating rules into runsets.
- Familiar with industry standard CAD tools flows for digital analog design
- Design Rule Development using Calibre (SVRF and TVF), or ICV (PXL) with exposure to VLSI design and execution.
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
Other Locations
US, TX, Austin; US, AZ, Phoenix; US, CA, Folsom; US, CA, Santa Clara
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
Annual Salary Range for jobs which could be performed in the US $146,520.00-$206,860.00
- Salary range dependent on a number of factors including location and experience
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
Salary : $146,520 - $206,860
