What are the responsibilities and job description for the Senior IP Logic Design Engineer position at Intel Corporation?
Job Description
Do Something Wonderful!
Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.
Who We Are
As part of Intel's Data Center Engineering Group, we develop cutting-edge IPs that serve as foundational components for the next generation of server processors. We specialize in the design and development of complex IP blocks and subsystems, with a strong emphasis on IO architecture
Who You Are
Your responsibilities include but not limited to:
You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Other Locations
US, Hillsboro
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
Annual Salary Range for jobs which could be performed in the US $161,230.00-$227,620.00
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
Do Something Wonderful!
Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.
Who We Are
As part of Intel's Data Center Engineering Group, we develop cutting-edge IPs that serve as foundational components for the next generation of server processors. We specialize in the design and development of complex IP blocks and subsystems, with a strong emphasis on IO architecture
Who You Are
Your responsibilities include but not limited to:
- Defines, documents and designs the microarchitecture of IP blocks and subsystems
- Owns the register transfer level (RTL) development for the IP block and implements the specification for logic components
- Ensures quality of design through clean design partitioning, clear microarchitectural documentation, reviewing RTL design and verification of features
- Applies various strategies, tools and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals
- Delivers microarchitecture specifications (MAS) document along with detailed clear block diagram, signal level description, clocking details, power and timing requirements to capture the implementation details and ensure correct interactions between blocks or Ips
- Reviews the verification plan and implementation to ensure design features are verified correctly and implements corrective measures for failing RTL tests to ensure correctness of features
- Supports SoC customers to ensure high quality integration and verification of the IP block
- Drives quality assurance compliance for smooth IP to SoC handoff
- Supports post-silicon activity to enable various features
- Good problem-solving ability
- Excellent technical leadership/teamwork/communication skills and a proven ability to work with dynamic schedules
You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
- Candidate should possess a Bachelor's Degree with at least 4 years of relevant experience in chip design with familiarity of the entire development flow from definition to tape-out – OR - Master's Degree in Electrical, Electronics or Computer Engineering with at least 3 years of relevant experience in chip design with familiarity of the entire development flow from definition to tape-out
- Knowledge of processor architecture, server hardware/software, and high-speed serial link protocols
- Expertise in System Verilog/OVM or UVM methodology and/or Formal Verification techniques
- System simulation models and debugging RTL/tests
- Experience in High-speed serial link protocols/IPs (PCIe, UPI, CXL, IOMMU etc)
- Experience in Computer architecture and PCIe, UPI, CXL, IOMMU, Cache Coherency protocols.
- Experience in authoring Functional Specifications
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Other Locations
US, Hillsboro
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
Annual Salary Range for jobs which could be performed in the US $161,230.00-$227,620.00
- Salary range dependent on a number of factors including location and experience
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
Salary : $161,230 - $227,620
