What are the responsibilities and job description for the SoC Design Engineer –Design For Debug Validation position at Intel Corporation?
Job Details
Job Description:
Come join Intel's Design Development Group organization as an SOC Validation engineering focused on Design for Debug (DFD). As a member of the product team, you will work firsthand with multi-function teams/sites, implementing and validating state-of-the-art debug solutions appropriate for new and existing technology in the product. In this role you will be working as part of a pre-silicon validation team for future Intel SoCs or IPs, focusing on debug validation. You will be working with pre-silicon and post -silicon validation teams to improve debug features and tools suites. You will also work closely with post-silicon validation SW teams on debug tool validation and silicon enabling. You will be pioneering new debug tools and flows, reviewing and publishing architectural specs and supporting next-generation silicon enabling on system platforms.
Your Responsibilities Will Include But Not Be Limited To
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
Business Group
The Client Engineering group (CEG) is a worldwide organization focused on the development and integration of SOCs, and critical IPs that power Intel's leadership products, driving the Client roadmap for CCG, and invest in future disruptive technologies.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://jobs.intel.com/en/benefits
Annual Salary Range for jobs which could be performed in the US:
$121,050.00-$170,890.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
Job Description:
Come join Intel's Design Development Group organization as an SOC Validation engineering focused on Design for Debug (DFD). As a member of the product team, you will work firsthand with multi-function teams/sites, implementing and validating state-of-the-art debug solutions appropriate for new and existing technology in the product. In this role you will be working as part of a pre-silicon validation team for future Intel SoCs or IPs, focusing on debug validation. You will be working with pre-silicon and post -silicon validation teams to improve debug features and tools suites. You will also work closely with post-silicon validation SW teams on debug tool validation and silicon enabling. You will be pioneering new debug tools and flows, reviewing and publishing architectural specs and supporting next-generation silicon enabling on system platforms.
Your Responsibilities Will Include But Not Be Limited To
- Validation of Design for Debug features (e.g. low & high-bandwidth signal tracing and event triggering) using simulation, emulation, and/or FPGA
- Creating test plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide
- Learning the Power Management, Memory and debug architecture and microarchitecture by debugging failures to the root cause
- Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design
- Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models
- Developing high level (for example, System C) modeling for RTL components
- Developing debugging tools and software
- Self-motivator with strong problem solving skills.
- Excellent interpersonal skills, including written and verbal communication.
- Ability to work as part of a team and collaborate in a high-paced atmosphere.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
- Bachelors Degree in Electrical Engineering, Computer Engineering, or related STEM degree and 3 years of industry experience
- OR Masters in Electrical Engineering, Computer Engineering or related STEM degree and 2 years of industry experience
- 3 years experience in the following;
- Experience with computer architecture
- Experience with Programming languages/Scripting: C, Perl, Verilog and UNIX* or Linux*
- Experience with writing validation plans and software to implement those validation plans
- Experience with reading and interpreting technical specs and Register Transfer Level (RTL) code
- Extensive Pre-silicon & Post-silicon Track record of driving debug tools enabling & validation, improvements and getting them adopted by others
- Proven record of working across validation teams to solve problems
- Expert of HW and SW Interaction and debug to root cause
- 3yrs experience with IA-32 assembly and/or Verilog* programming experience
- 3yrs experience with validation or testing experience, especially in a silicon design team
- 2yrs experience with industry standards such as ATB/Coresight, JTAG
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
Business Group
The Client Engineering group (CEG) is a worldwide organization focused on the development and integration of SOCs, and critical IPs that power Intel's leadership products, driving the Client roadmap for CCG, and invest in future disruptive technologies.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://jobs.intel.com/en/benefits
Annual Salary Range for jobs which could be performed in the US:
$121,050.00-$170,890.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
Salary : $121,050 - $170,890
