What are the responsibilities and job description for the Sr. Timing Signoff and Methodology Lead position at Intel Corporation?
When you join Intel, you become part of a global organization with big ambitions. Our people have had a profound influence on the world by creating radical innovations that revolutionize the way we live.
We are driven by our purpose: To create world-changing technology that improves the life of every person on the planet. We develop technologies that bring down barriers and enable tomorrow’s greatest scientific breakthroughs and cultural achievements.
Responsibilities Include But Are Not Limited To
Minimum Qualifications
We are driven by our purpose: To create world-changing technology that improves the life of every person on the planet. We develop technologies that bring down barriers and enable tomorrow’s greatest scientific breakthroughs and cultural achievements.
Responsibilities Include But Are Not Limited To
- Performs timing analysis and timing optimization, generates, and verifies timing constraints, and fixes timing violations at full chip/block level for SoCs.
- Conducts timing rollups, designs for functionality, and develops performance and power optimized clock networks.
- Develops and defines methodologies to ensure highest quality of timing models that enable the physical design team to operate efficiently.
- Defines the right process, voltage, and temperature (PVT) conditions to be used for timing analysis for a given design based on the product plans such as operating conditions and binning.
- Works closely with the clocking team and other backend full chip designers for clocking balance, timing fixes, power delivery, and partitioning.
- Collaborates with architecture, clocking design, and logic design teams to deliver flow development for chip integration and validates high performance low power clock network guidelines.
- Understanding of DFT (design for testability) logic and hands-on experience in design closure.
Minimum Qualifications
- Bachelor's degree in Electrical / Computer Engineering, Computer Science or in a STEM related field of study.
- 8 years of timing verification experience.
- Master's degree
- 10 years STA hands on experience.
- Server experience.