What are the responsibilities and job description for the DFT Engineer position at Intel?
Job Description
Advanced Design is always the first design team at Intel tackling the challenges of scaling technology to the cadence of Moores Law. We work with industry leading design and process technologists to enable breakthroughs in power, performance, and density as we enable our product design partners to bring world-class products to the market. Join us for a fast-paced, dynamic, and richly rewarding experience on the forefront of technology.
The SOC Debug Engineer role has a single purpose which is to solve our most challenging product issues. SOC Debug Engineers work with our internal product teams (Manufacturing / Validation / Software) and our customer teams during critical escalations to root cause system level failures and / or anomalies directly impacting our customers or jeopardizing our committed timelines. They are responsible for performing low level and complex debug across multiple IP and system domains within a product, and will use their experience with / understanding of SOC design and architecture, Firmware, Bios and software to completely understand any issue and drive a resolution. They are also expected to drive innovative debug capability improvements through new Design for Debug (DFD), debug tools and scripts to continuously improve the debug discipline.
As an SoC Debug Engineer you will work on :
- Develops and supports design for test (DFT) structures.
- Determines design for test approaches and develops DFT architecture.
- Contribute to insertion / verification flow development.
- Designs and verifies DFT structures for memories (MBIST), digital and analog circuitry.
- Performs scan synthesis.
- Creates, simulates, and verifies automatic generated test patterns (ATPG).
- Creates functional tests and corresponding test patterns.
- Supports silicon bring up of test patterns.
- Perform logic design and verification.
- Generate test patterns and provide consultation to post-silicon key stakeholders.
- Performs diagnosis of test patterns on silicon and optimizes test time.
Design Enablement.
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications :
Candidate must BS degree with 4 years of experience or MS degree with 2 years of experience or PhD degree with 1 years of experience in Electrical Engineering, Computer Engineering, Computer Science Engineer or related field.
4 years of experience in the following :
Preferred Qualifications :
5 years of experience in the following :
Inside this Business Group
As the worlds largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art - from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly / test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
Other Locations
US, TX, Austin; US, AZ, Phoenix; US, CA, Folsom; US, CA, Santa Clara
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
Annual Salary Range for jobs which could be performed in US, California : $139,480.00-$209,760.00
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
JobType
Hybrid
Salary : $139,480 - $209,760
