Analog Design Verification Engineer

Role: Analog Design Verification Engineer

Location: Dallas, TX - Onsite

Duration: 12 Months

**No C2C**

We are seeking an experienced Analog Design Verification Engineer to join our client team. The ideal candidate will have a strong understanding of analog mixed-signal (V-AMS) verification methodologies and System Verilog/UVM for functional, parametric, and DFT/reliability testing. This role involves developing test benches, creating verification plans, running simulations, debugging failures, and ensuring verification coverage closure.

Key Responsibilities:

• Develop a deep understanding of analog mixed-signal (AMS) blocks to effectively control and verify their functionality using V-AMS.
• Learn and analyze the testbench architecture, ensuring robust verification methodologies.
• Understand the DIGTOP block (which includes an Arm M0 processor and an analog front end) to create appropriate verification strategies.
• Develop and execute test sequences based on high-level descriptions.
• Implement and execute functional, parametric, and DFT/reliability tests.
• Develop and integrate monitors to verify expected performance.
• Perform corner simulations, analyze results, and report findings.
• Review waveforms in SimVision, create SVCF files, and share insights with the team.
• Provide weekly status reports and collaborate with cross-functional teams.

Qualifications & Skills:

• 8 years of experience in Analog Mixed-Signal (V-AMS) verification.
• 5 years of experience with SystemVerilog/UVM verification methodologies.
• Hands-on experience with LBC10 devices, DIGTOP blocks (including Arm M0 processor), and analog front-end components (such as Type-C detection logic, power paths, OVP/UVP/current limits).
• Expertise in the full verification lifecycle, including:
• Developing test plans
• Creating and integrating BFM, Driver, Monitor, and Scoreboard components
• Performing stress/corner testing and failure debugging
• Conducting gate-level simulations and assertion-based verification
• Ensuring functional coverage closure