What are the responsibilities and job description for the Onsite Mid-level Verification Engineer, UVM, SystemVerilog position at Intelliswift Software Inc?
Job Details
Mid-level Verification Engineer with 5-8 years of experience of pure verification in FPGA.
This is a pure Verification Engineer role.
This position is onsite in the greater San Jose Bay Area.
What you will be doing:
- Purely verification of FPGA
- Programming using SystemVerilog
- Develop OO testbench infrastructure
- Develop test cases using UVM
- Scripting
What you will need:
- 5-8 years in pure Verification
- Solid in SystemVerilog programming
- Experience with UVM, Universal Verification Methodology
- Experience developing OO testbench infrastructure
- Experience with Interfaces such as I2C - Inter-Integrated Circuit, MDIO - Management Data Input/Output, SPI - Serial Peripheral Interface, PCIe - Peripheral Component Interconnect Express
- Scripting using Python or Perl
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