FPGA Design Engineer

Description

Leidos Defense Sector is seeking a talented FPGA Design Engineer to join a diverse team to create unique solutions for complex problems.

The engineer's primary job functions include architecting, implementing, and testing firmware solutions targeting FPGAs and their supporting circuitry. Additional skills to assist design teams with circuit and PCBA design and analysis, embedded processor/microcontroller or SoC designs, technical trade studies, and evaluation of technology improvements are a plus. Experience designing and implementing DSP functions is desired.

The applicant must have experience implementing FPGA designs using VHDL in Xilinx Vivado. Must have experience optimizing FPGA designs for resource utilization, power consumption, and performance. Experience with timing closure techniques and methodologies, including timing constraints. Must have experience writing test benches for simulation of FPGA designs ensuring correct behavior, performance, and timing. Experience with ModelSim is desired. Strong understanding of digital design principles, FPGA architectures, and high-speed communication protocols.

Basic Qualifications:

• Bachelor's degree in Electrical Engineer, Computer Engineering, Computer Science, Software Engineering or a related discipline from an ABET-accredited institution with 12 years of relevant experience or 10 years with MS degree.
• Experience with embedded Software/Firmware design.
• High proficiency with C/C , VHDL, and TCL.
• Experience in FPGA system design and test from architecture through implementation.
• Familiarity with modern Xilinx FPGA families and design tools (7-series FPGAs, Ultrascale , Vivado, Xilinx IP cores).
• Experience with multiple high-speed serial communication standards and interfaces (e.g. Aurora, 10Ge, PCIe, DDR4/3/2/1, JESD204B).
• Experience with digital signal processing (DSP)
• Experience developing and implementing FPGA-optimized versions of DSP algorithms (e.g. modulation/demodulation, PLLs, filters, image processing).
• Experience with standard internal interfaces such as AXI4, AXI4-Stream, AXI4-Lite.
• Motivated self-starter and problem solver with experience executing in multi-disciplinary teams.
• Hands-on laboratory experience with instrumentation, test equipment, and debug/test methods.
• Candidate must be a resident of or be willing to relocate to the Shalimar FL area.

Other Qualifications:

Preference shown to candidates who possess:

• Master's degree in Electrical Engineer, Computer Engineering, Computer Science, Software Engineering or a related discipline from an ABET-accredited institution.
• 15 years of relevant experience.
• Experience working with SoC designs such as Zynq and Zynq Ultrascale including architecting and interfacing with peripherals, interrupts, and related bus architectures.
• Experience working with embedded operating systems.
• Working knowledge of digital/analog/mixed signal electronics, components, and interface/communication standards.
• Experience with FPGA PCBA hardware design.
  

Original Posting: April 10, 2025
For U.S. Positions: While subject to change based on business needs, Leidos reasonably anticipates that this job requisition will remain open for at least 3 days with an anticipated close date of no earlier than 3 days after the original posting date as listed above.

Pay Range: Pay Range $126,100.00 - $227,950.00

The Leidos pay range for this job level is a general guideline only and not a guarantee of compensation or salary. Additional factors considered in extending an offer include (but are not limited to) responsibilities of the job, education, experience, knowledge, skills, and abilities, as well as internal equity, alignment with market data, applicable bargaining agreement (if any), or other law.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.