What are the responsibilities and job description for the ASIC Design Engineer - New College Grad 2025 position at Lensa?
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As a member of our digital logic interconnect design team, you will be responsible for implementing logic for our next-generation GPU's and SOCs which enable high-performance interconnect of multi-GPU/CPU/DPU system topologies for autonomous machines, Cloud and Data Centers, Deep learning, High-Performance Computing, Gaming, and Entertainment solutions. Tasks will include micro-architectural definition, RTL coding, logic debug, timing closure, power optimization and verification support. The ideal candidate will have 10 years of direct experience with PCIE Physical/Datal-Link Layer or other industry standard protocols like CXL, AXI, CHI, UCIe USB, SATA.
What You'll Be Doing
The base salary range is 96,000 USD - 212,750 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
You will also be eligible for equity and benefits (https://www.nvidia.com/en-us/benefits/) . NVIDIA accepts applications on an ongoing basis.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
As a member of our digital logic interconnect design team, you will be responsible for implementing logic for our next-generation GPU's and SOCs which enable high-performance interconnect of multi-GPU/CPU/DPU system topologies for autonomous machines, Cloud and Data Centers, Deep learning, High-Performance Computing, Gaming, and Entertainment solutions. Tasks will include micro-architectural definition, RTL coding, logic debug, timing closure, power optimization and verification support. The ideal candidate will have 10 years of direct experience with PCIE Physical/Datal-Link Layer or other industry standard protocols like CXL, AXI, CHI, UCIe USB, SATA.
What You'll Be Doing
- Micro architecting the next generation of PCIE PL and DL
- Implementing readable, high-performance, area and power efficient RTL to achieve design targets, including upcoming performance, adaptability, and safety industry standards
- Collaborating with architects, external partners, software engineers and circuit designers to deliver best in class IP
- Partnering with our Physical Design team on partitioning, floorplanning and timing closure
- Providing design documentation, triaging and debugging functional and performance bugs, integration and infrastructure support and development
- Bachelors Degree in EE, CS or CE
- Experience in coding PCIE PL/DL logic or lower layers of the OSI stack in general
- in-depth understanding of physical design
- Strong working knowledge of Verilog or System Verilog
- Strong collaboration and communication skills
- Good knowledge of PCIe PL/DL sub blocks such as: data scrambling, packet framing, NRZ/PAM4 encoding, equalization, TLPs/DLLPs, LTSSM, power states, errors, etc
- Knowledge of alternate protocol negotiation, CXL/UCIe would be an added advantage
- Experience in handling post-silicon bringup, and good understanding of signal integrity concepts
- Understanding of firmware/driver structures and their interaction with HW
The base salary range is 96,000 USD - 212,750 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
You will also be eligible for equity and benefits (https://www.nvidia.com/en-us/benefits/) . NVIDIA accepts applications on an ongoing basis.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
