What are the responsibilities and job description for the Sr. Staff Design Verification Engineer position at Lightmatter?
Lightmatter is revolutionizing AI data center infrastructure, enabling significant advancements in human progress. The company pioneered the world's first 3D-stacked photonics engine, Passage, capable of connecting thousands to millions of processors at the speed of light in extreme-scale data centers for the most advanced AI and HPC workloads.
We will continue to accelerate the development of data center photonics and grow every department at Lightmatter. If you're passionate about tackling complex challenges, making an impact, and being an expert in your craft, you'll find yourself at the heart of a dynamic, interdisciplinary team.
Your role as Design Verification Engineer involves close collaboration with digital design experts, using UVM testbench techniques to rigorously verify their designs. Your responsibilities include working alongside photonic and analog designers, gaining a deep understanding of their innovative designs, and applying Real Number Modeling (RNM) and AMS verification methods.
Key Responsibilities:
- Engage collaboratively with teams specializing in digital, photonics, and analog design to develop comprehensive test plans.
- Design and implement UVM testbenches for both subsystem-level and full-chip verification, including debugging testbenches, resolving issues, achieving high coverage, and overseeing the final sign-off on Design Verification (DV).
- Develop Real Number Models (RNM) for photonics and analog circuits, conduct AMS verification in conjunction with UVM, and ensure precise model representation. Contribute significantly to the development of the Golden Reference Model (GRM) for design verification.
Qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field, or equivalent experience.
- 12 years of design verification and SystemVerilog experience.
- 2 years of experience in Python.
- Expertise in developing the UVM library.
- Experience with simulators such as Xcelium, ModelSim, Questa, or VCS.
Preferred Qualifications:
- Master's degree or higher in Electrical Engineering, Computer Engineering, or related field, or equivalent experience with 8 years of design verification and SystemVerilog experience.
- Knowledgeable about assertion languages, power verification, reset-domain crossing verification, and AMS verification.
- Strong problem solver, communicator, and team player with the ability to work with teams across multiple sites.
- Ability to react to change and thrive in a fast-paced environment.
- Communicates complex concepts effectively to diverse stakeholders, fostering support and consensus for initiatives.
- Previous leadership experience.
Benefits:
- Comprehensive Health Care Plan.
- Retirement Savings Matching Program.
- Life Insurance.
- Generous Time Off.
- Paid Family Leave.
- Short Term & Long Term Disability.
- Training & Development.
- Commuter Benefits.
- Flexible, hybrid workplace model.
- Equity grants.
