What are the responsibilities and job description for the Design verification Engineer - Full Time - Sunnyvale, CA or Austin, TX (Onsite) position at Lorven Technologies, Inc.?
Job Details
Hi,
Our client is looking Design verification Engineer for Full Time project in Sunnyvale, CA or Austin, TX (Onsite). below is the detailed requirements.
Job Title : Design verification Engineer
Location : Sunnyvale, CA or Austin, TX (Onsite)
Duration : Full Time
Job Description:
- Design Verification Engineering Services
- Testbench development System Verilog Universal Methodology ("UVM"), Python, and C tests
- Integration/development of C tests/Application Programming Interface ("APIs") and software build flow
- Integration of UVM testbenches
- Test development and debug, including without limitation tests for functionality, power, performance, error, and connectivity, both for RTL and Gate Level Netlist Design Under Test, tests for functional and code coverage improvements
- Coverage collection and closure
- Documentation of tests, testbench, use-cases, exclusions, and status
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