Director, Design Verification

The Switch Business Unit in Marvell designs and develops the next generation datacenter and enterprise System-On-Chip switch processors on leading edge process technology. We develop the architecture, collaborate on IP development, create the physical design, and work with the world’s leading data center and enterprise companies to bring next generation networking to reality.

• Build and manage a strong digital design verification team.
• Improve the design methodology and flow.
• Makes decisions for talent management activities including hiring, assessing, rewarding, retaining, and developing engineers.
• Lead and be a part of highly technical team developing best-in-class high complexity products.
• Perform design review, code review, and apply tools to formally check/fix RTL against various design rules.
• Work with the verification team to define verification strategy, test-plan, analyze and sign-of verification coverage.
• Cooperate with Synthesis, DFT, STA, PnR to implement subsystems that meet challenging PPA requirements.
• Support Emulation, functional ATE, and silicon validation teams.

• At least 5 years of experience in direct management of multidisciplinary teams including design, validation etc. (global team management is a plus)
• Proven leadership and problem solving skills focusing on uncompromised quality, innovation and continuous learning and improvement
• Strong communication, collaboration and teamwork skills and ability to work in global team environment
• Ability to build plans and define immediate and future needs based on project requirements

• Bachelor’s degree in Electrical Engineering or related fields and 12 years of related professional experience in Design Verification for VLSI designs, OR Master’s degree in Electrical Engineering or related fields with 10 years of experience in Design verification for VLSI designs
• Hands-on micro architecture and RTL coding experience, Verilog/SV preferred.
• Strong knowledge of verification methodology, logic synthesis, DFT, and timing analysis.
• Excellent problem-solving skills and out-of-the-box thinking to oversee design failures.
• Experiences in PCIe/Ethernet is preferred.
• Experiences in UVM verification methodology is preferred.
• Very familiar with digital design methodologies, understand all stages of ASIC design flows, and experienced with state-of-the-art design verification EDA tools.

176,930 - 265,000, $ per annum At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process. This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office. #LI-AB4