What are the responsibilities and job description for the (2025 Summer Intern)-Design for Testing (DFT) position at MediaTek?
MediaTek is the world’s 4th largest global fabless semiconductor company and powers more than 2 billion devices a year.
We lead the market in chipset sales for Smartphone, Smart TVs, Voice Assistant Devices (VAD), Android tablets, feature phones, and optical disc products. We build chips that are less about connecting people to their devices and more about connecting your devices to what matters. Connecting to the things that shape our lives, makes us smarter, healthier and improve everyday life.
You may not know it, but our chips and technology are already likely part of your everyday life. You will find us in 20 percent of homes globally and nearly 1 of every 3 mobile phones is powered by MediaTek.
Apply now and help shape the future of chip design!
We are currently seeking Design for Testing (DFT) Intern. Roles and responsibilities include:
- Develop scripts to improve ATPG flow
- Responsible for setting up and running ATPG/Scan-insertion, pattern generation for IP
- Responsible for Gate Level verification of DFT patterns
- Responsible for setting up and port DFT patterns from IP level to SOC level
Required Course Works
- VLSI design, Digital logic design, Integrated circuits, Design for Test
Qualifications:
- Candidate must be pursuing Masters or PhD in Electrical/Computer Engineering
- Be very familiar of programming and scripting languages like Perl, Tcl, Python
- Solid understanding/skills/experience of high level description languages such as Verilog or VHDL, and synthesis of RTL
Preferred qualifications:
- candidate has previous industry work experience is highly preferable
- candidate has good understanding of ARM architecture is preferable
- candidate has taken classes in VLSI design, Digital logic design, Integrated circuits, Design for Test
