Demo

Layout Designer

Mindlance
Santa Clara, CA Full Time
POSTED ON 4/14/2025
AVAILABLE BEFORE 5/11/2025

Mask Layout Designer

Summary

Our teams are responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and bandgap references. We are working on new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF / Analog architecture and design, Systems / PHY / MAC architecture and design, VLSI / RTL design and integration, Emulation, Design Verification, Test and Validation, and FW / SW engineering. In this role, you will work closely with the design team to layout and verify custom RF and analog IP for complex SoC products. You will have a critical impact on developing Client’s state-of-the-art designs and getting them into hundreds of millions of products.

Description

As an IC Layout Engineer, you will be a key member of our team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes. Responsibilities include : - Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC / DAC, baseband filters, and bandgap / bias / LDO. - Block level layout through full verification flow including extraction, DRC, LVS, and DFM checking. - Co-work with designers on block level floorplanning. - Layout review for power / gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.

Minimum Qualifications

  • BS and 5 years of relevant industry experience.
  • FinFet experience

Preferred Qualifications

  • Experience in custom RF / analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS.
  • Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing.
  • Solid understanding of RC delay, electromigration, and coupling.
  • Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, etc.
  • High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. in FinFet Technology (7nm experience highly preferred)
  • Knowledge of CADENCE layout tools.
  • Excellent communication skills and able to work with cross-functional teams.
  • Scripting skills in PERL or SKILL are a plus, but not required.
  • Mindlance is an Equal Opportunity Employer and does not discriminate in employment on the basis of – Minority / Gender / Disability / Religion / LGBTQI / Age / Veterans.”

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