Demo

Sr STA engineer

Mirafra Technologies
San Jose, CA Full Time
POSTED ON 4/3/2025
AVAILABLE BEFORE 5/2/2025
  • Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
  • Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
  • Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
  • Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
  • Leading the fullchip clocking design including diagrams and related documentation.

Preferred Qualifications:

  • Experience in Static Timing Analysis.
  • Experience with constraint analyzer tools such as Fishtail/TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence).
  • Experience with Spyglass CDC and glitch analysis.
  • Experience with STA tools such as PrimeTime/Tempus.

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