System Verification Engineer

I would like to set up a time to discuss the potential opportunity below:

Role: Verification Engineer

Location: Longmont, CO – 80503

Duration: 5 months (with possible extension)

Job duties:

• Participate in design and functional verification of a block(s) of IP. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block and overall system.
• Be responsible for developing and improving simulation test environments consisting of directed and constrained-random tests to be run during simulation.
• Be expected to adopt the evolving verification methodologies used in the industry to functionally and work within the existing verification infrastructure. Be familiar with hardware modeling and/or assertion-based verification methods.

Experience:

• 3 or more years of proven verification experience on Verilog and System Verilog for IP development and verification required
• Familiar with UVM verification methodologies and environments
• Strong debug skills
• Experience with simulation tools ModelSim/VCS and VIPs
• Experience in Verilog/SystemVerilog
• Strong analytical skills and attention to detail
• Excellent written and communication skills
• AMD/Xilinx FPGA and tools experience is a bonus

Essential skills: RTL verification experience, Verilog/System Verilog, ModelSim/VCS, UVM

Nice-to-have skills: FPGA Experience (Xilinx/AMD FPGA preferred), Vivado experience