Design Verification Engineer

Role: Design Verification Engineer (GPU) 

Company: Samsung 

Location: San Jose, CA

Notes:

- Current state-of-the-art testbench development such as UVM methodology

- Experience in design verification with UVM and SystemVerilog is a MUST

Technical:

As a Design Verification Engineer, you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems.

Responsibilities:

• Triage regression failures and make testbench updates

• Debug functional errors in the RTL model using simulation and debug tools.

• Maintain efficient and clean regression status

• Develop Scalable SystemVerilog/UVM test benches for unit-level and/or Cluster level verification.

• Review Architecture and Micro-Architecture specifications.

• Closely work with Architects and RTL designers.

• Define, maintain, and execute unit-level and/or Cluster level verification test plans.

• Generate and run test cases on logic simulation models.

• Code Functional coverage models and System Verilog assertions.

• Drive Functional Coverage and Code coverage to closure.

Requirements:

• 5-15 years of industry experience in a design verification role.

• Proficient in System Verilog/UVM/OVM, OOP/C

• Knowledge of GPU, experience with Shader, Texture, or Memory System a plus

• Experience with code coverage and functional coverage-driven verification methodology.

• Experience in creating, running, and debugging of SystemVerilog/UVM constraint-random Testbench.

• Excellent working knowledge of scripting languages such as Python or Perl.

• Understanding of micro-architecture, logic design, FSMs, and arithmetic datapath pipelines.

• Strong functional verification experience including Test planning, Testbench Architecture, and Test/Coverage Model/Assertion Development.

• Strong debugging skills

• Strong programming skills with a good understanding of algorithms and data structures

• Good verbal and written communication skills.