What are the responsibilities and job description for the RF Layout Engineer (Transistors) position at Oxford Global Resources?
Job Details
Job Title: RF Layout Engineer (GaN or LDMOS RF transistors)
Location: Onsite Chandler, AZ
Start Date: 12/8 - possible to start in January
Duration: 6-12 months
Process: 2 virtual interviews
Role Summary: Interfacing with 1 other layout resource, designers, Device and product engineering teams, process engineering and manufacturing teams to generate accurate high-power transistors. Matching structure layouts that meet customer needs. on average doing 1 tapeout per week.
Key Responsibilities: creating device layouts using Cadence tools and other EDA tools like Mentor Calibre, building custom RF transistors and devices to support RF Product team. Testing of structures using cell hierarchy- DRC- design rule checks, maintaining libraries and conducting layout reviews. this work will include both GaN, Gallium Nitride, and LDMOS technologies. Cadence work will be done through Linux environment.
Qualifications: RF transistor layout, experience with GaN or LDMOS technologies, Cadence layout tools, SKILL coding, knowledge of device physics and semiconductor wafer processing and tape outs.
