What are the responsibilities and job description for the Defense FPGA Verfication Engineer (UVM)- Active Secret -RELO Boston ,MA position at Pacific Technical Resources LLC?
Pacific Technical Resources, LLC.IT / Engineering Recruitment Professionals"Helping to build Great Companies and Great Lives" Hiring! Direct hire Defense Sr FPGA Verification Engineer (UVM) with Active Secret Clearance for aBillion Dollar Leader in the Defense Industry in Boston, Massachusetts area(Dedham) As a Senior Cyber FPGA Design Verification engineer, you’ll be a member of a cross functional team responsible for product design from system architecture & requirements allocation through product release and production of cost-sensitive secure products. Experience with OVM / UVM design verification methodology : bash / csh, Perl, TCL, Python or similar scripting languages; VHDL or similar hardware description languages. REQUIREMENTSBachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field and 8 years of relevant experienceOR Master's degree plus 6 years of relevant experience. Start 2025 with a great new direct hire career with this Defense leader. If qualified and open to Boston, Massachusetts area please send your resume today toClara at cfoo@pacifictechnicalresources.com If you are qualified and willing to relocate and seeking a new career opportunity please send your resume to Clara at cfoo@pacifictechnicalresources.com Pacific Technical Resources, LLC. specializes in IT / Engineering Recruitment Placement with roots from Honolulu, Hawaii is headquartered in Phoenix, Arizona. We bring extensive experience with IT / Engineering recruitment along with a holistic philosophy of valuing people. We have special industry expertise with Energy Solutions and Aerospace / Defense. Please visit us on our website at www.pacifictechnicalresources.com
