What are the responsibilities and job description for the Analog Layout Engineer position at PDDN INC.?
Job Description
Role: Analog Layout Engineer
Location: Santa Clara, CA
Interview: Phone/Skype
Job Type: Contract
Job Description:
Senior layout designer responsible for layout of high-performance analog cores such as analog-to-digital converters, digital-to-analog converters, PLL, transceivers, etc. Leading IC layout of cutting-edge high-performance, high-speed #CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm, 16nm.
Qualifications:
Thorough knowledge of industry standard EDA tools from Cadence, Mentor, and Synopsys.
Ability to set up LVS, #DRC, ERC environments and debug verification issues using Cadence and Mentor tools.
Experience with high-performance analog blocks (ADCs, DACs, PLLs, etc.)
Experience in floor planning, block level routing, and top-level chip assembly.
Knowledge of high-performance analog layout techniques.
10 years of experience in high-performance analog layout in advanced CMOS processes.
Experience with #FinFET process nodes preferred.
Strong written and verbal communication skills.
🔹 Eligibility Criteria:
✔️ Genuine H1B candidates with verifiable I-94 travel history (C2C acceptable).
✔️ Green Card & US Citizens will be considered only on W2 payment terms.
🚀 If you or someone you know is a strong match, let's connect immediately!
Skills: #AnalogLayout #EDAtools #Cadence #Mentor #Synopsys #LVS #DRC #ERC #CMOS #HighPerformanceLayout
Additional Information
All your information will be kept confidential according to EEO guidelines.
