What are the responsibilities and job description for the ASIC/SoC Design Verification Engineer position at PER International?
We are partnering with a high-growth startup at the forefront of semiconductor innovation. This company is redefining edge AI computing with cutting-edge technology and a highly talented team. Backed by strong funding and industry-leading expertise, they offer an exciting opportunity for engineers to work on next-generation SoC designs. With a culture of innovation, collaboration, and technical excellence, this is the perfect environment for engineers looking to make a significant impact in a fast-moving industry.
We are seeking a highly skilled and motivated SoC Design Verification Engineer to join our team. This role involves working closely with design engineers and architects to ensure the successful verification of complex SoC designs. The ideal candidate will have extensive experience in test planning, automation, and debugging, as well as a strong background in verification methodologies and scripting.
Qualifications & Requirements:
• Collaborate with design engineers and architects to define, document, and implement detailed test plans for SoC design verification.
• Build and maintain infrastructure and automation environments for verifying SoC architecture, functionality, and performance.
• Develop reusable testbenches, constrained-random and directed test cases, and behavioral modules for both block-level and system-level verification.
• Develop regression strategies, methodologies, and tools (scripts) to automate and optimize the verification process.
• Define and measure functional coverage, ensuring verification closure for design releases and tape-out.
• MS with 8 years of relevant experience or PhD with 3 years of experience in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• In-depth knowledge of UVM/OVM, semiformal verification, assertion-based verification, and hardware/software co-verification methodologies.
• Extensive experience in building verification infrastructure, test planning, coverage closure, and testbench/test case development for functional and performance verification.
• Proficiency in Verilog, SystemVerilog, Python/Perl/TCL/Shell scripting, C/C , SystemC, and mainstream ISAs assembly coding.
• Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocols, and RISC-V/ARM or DSP core architectures.
• Experience in verifying designs at both RTL and post-P&R gate levels.
• Ability to work in a dynamic startup environment, independently and collaboratively, with strong technical leadership skills.
Preferred Experience:
• Working knowledge of AI/ML computing, GPU, ISP architectures, and accelerators.
• Experience in verifying mixed-signal designs and interfaces between digital and analog components.
• Experience in verifying high-speed IO interfaces such as PCIe and DDR.
INTERESTED?
We are committed to submitting suitable candidates for this vacancy to our client ASAP, for more information contact Renz Moreno at PER Recruitment or send your CV to renz@per-international.com
