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Memory Circuit Design Engineer

PER International
Fremont, CA Full Time
POSTED ON 2/20/2025
AVAILABLE BEFORE 3/20/2025

Job Summary:


The Memory Circuit Design Engineer will be responsible for designing memory IC projects, from initial concept to tape-out, ensuring smooth development processes. This engineer will focus on optimizing speed, power efficiency, and silicon area utilization while collaborating with cross-functional teams to enhance the overall performance of memory designs.


Key Responsibilities:


  • Design memory IC projects from initial concept to tape-out, ensuring a smooth and successful development process
  • Define and implement memory architectures and circuits, focusing on optimizing speed, power efficiency, and silicon area utilization
  • Create comprehensive test plans to thoroughly evaluate memory designs, using simulation tools and methodologies to validate functionality and performance
  • Identify and troubleshoot design issues using simulation and analysis to isolate problems and develop effective solutions
  • Collaborate with cross-functional teams to analyze and enhance memory design performance, addressing bottlenecks and ensuring optimal operation
  • Work closely with analog and digital engineering teams to ensure seamless integration of memory designs into overall product development, maintaining compatibility and functionality
  • Investigate and resolve design-related issues, contributing to silicon bring-up and validation activities for memory ICs
  • Stay current with industry advancements in memory design, implementing cutting-edge techniques and technologies
  • Implement rigorous testing and validation processes to ensure memory designs meet quality and reliability standards
  • Maintain detailed documentation of memory design processes, methodologies, and findings to support team collaboration and project continuity


Qualifications & Requirements:


  • MS or PhD in Electrical Engineering with an emphasis on CMOS memory, digital, or mixed-signal design
  • 5 years of experience in circuit design in advanced CMOS processes (PhD experience may be considered as experience), with successful tape-out experience at leading foundries
  • Experience in memory circuit design in one of the following: SRAM, DRAM, Flash, or emerging NVM technologies
  • Strong understanding of layout design, including layout-dependent effects, pitch matching, and design for manufacturing
  • Familiar with common EDA tools, CAD tools, and memory design methodologies (e.g., Synopsys, Cadence, Mentor Graphics)
  • Ability to create innovative architecture and circuit solutions to meet customer requirements
  • Ability to work in a startup environment and work both independently and as a team player


Preferred Experience:


  • Hands-on production experience with key memory blocks such as sense amplifiers, charge pumps, read/write assist circuits, PVT trackers, and power gating
  • Familiar with memory controllers or memory interfaces
  • Experience with emerging non-volatile memory (NVM) technologies


Company Overview:


We are partnering with a high-growth startup at the forefront of semiconductor innovation. This company is redefining edge AI computing with cutting-edge technology and a highly talented team. Backed by strong funding and industry-leading expertise, they offer an exciting opportunity for engineers to work on next-generation SoC designs. With a culture of innovation, collaboration, and technical excellence, this is the perfect environment for engineers looking to make a significant impact in a fast-moving industry.



This is an exciting opportunity to contribute to cutting-edge SoC design in a fast-paced and innovative environment. If you have a passion for advanced semiconductor technologies and thrive in a collaborative setting, we encourage you to apply.


To apply for this opening or to find out more about our other opportunities, please contact Georgie Rose on LinkedIn or send an email to Georgie@per-international.com

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