What are the responsibilities and job description for the Digital Design Verification Engineer position at PRI Global?
Job Title: Design Verification Engineer
Duration: 12 months
Location: Remote
Summary: Experienced Design Verification Engineer required with expertise in Verilog, System Verilog, C/C based verification, and UVM methodology. Proficient engineers with a Bachelor's degree in Computer Science, Computer Engineering, or equivalent practical experience will be considered.
Responsibilities:
- Design verification of complex digital circuits using Verilog, System Verilog, and C/C .
- Implementation of UVM (Universal Verification Methodology) for efficient verification.
- Collaboration with cross-functional teams to ensure design quality and performance.
- Identification and resolution of critical design issues.
- Development and maintenance of verification environments.
