What are the responsibilities and job description for the Design Verification Engineer (SOC/IP) position at Prodapt North America?
Job Details
Onsite Opportunity in Austin, TX
2 year project
Responsibilities:
- Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification.
- Develop functional tests based on verification test plan.
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
- Debug, root-cause and resolve functional failures in the design, partnering with the Design team.
- Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
- Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.
Requirements:
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
- 8 years of hands-on experience in SystemVerilog/UVM methodology and/or C/C based verification.
- Track record of 'first-pass success' in ASIC development cycles.
- 8 years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.
- Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.
- Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.
Cody Petritz
Sr. Technical Recruiter
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