What are the responsibilities and job description for the Senior Physical Design Engineer (Full-Chip Expertise) position at Prohires?
Job Details
Job Title: Senior Physical Design Engineer (Full-Chip Expertise)
Location: [Bay area, Austin] [Hybrid]
Experience: 7 years
Key Responsibilities:
Lead and execute full-chip physical design activities, including floorplanning, placement, clock tree synthesis (CTS), routing, and signoff.
Develop and implement physical design methodologies to achieve power, performance, and area (PPA) targets.
Perform timing closure and optimize designs for setup, hold, and other timing constraints.
Conduct power analysis and implement low-power design techniques, including power gating, multi-Vt optimization, and clock gating.
Perform physical verification (DRC, LVS, ERC) and ensure design manufacturability.
Collaborate with RTL design, verification, and architecture teams to resolve design issues and meet project goals.
Mentor junior engineers and contribute to the continuous improvement of physical design processes.
Work on advanced process nodes (e.g., 7nm, 5nm, 3nm) and address challenges related to scaling, variability, and parasitics.
Qualifications:
7 years of hands-on experience in full-chip physical design.
Strong expertise in EDA tools such as Cadence Innovus, Synopsys ICC2/Fusion Compiler, or equivalent.
Proficiency in timing analysis and optimization using tools like PrimeTime.
Experience with physical verification tools (e.g., Calibre, ICV) and signoff methodologies.
Knowledge of low-power design techniques and tools (e.g., UPF/CPF).
Familiarity with advanced process nodes and their specific challenges (e.g., finFET, multi-patterning).
Strong scripting skills in Tcl, Python, or Perl for automation and flow development.
Excellent problem-solving skills and attention to detail.
Strong communication and teamwork skills.
Thanks & Regards,
