Design Verification Engineer

We are hiring for our client - Mega Cloud Lab.

We are seeking a highly skilled Design Verification Engineer to join our team. As a Design Verification Engineer, you will be responsible for developing and executing comprehensive verification environments to ensure the quality and functionality of our complex digital designs.

Key Responsibilities

• Design and implement scalable, configurable, and reusable verification environments using SystemVerilog and UVM.
• Develop SystemVerilog and/or SystemC models for simulation.
• Create and maintain UVM testbenches, including test plans, test cases, and coverage models.
• Apply constrained-random verification methodologies to achieve high functional coverage.
• Analyze simulation results and debug design issues.
• Collaborate with design engineers to improve design quality and testability.
• Stay up-to-date with the latest verification methodologies and tools.
  
  

Required Skills And Experience

• Strong proficiency in SystemVerilog and UVM.
• Experience with digital design and verification methodologies.
• Experience with industry-standard verification tools (e.g., Synopsys VCS, Cadence Xcelium).
• Strong problem-solving and analytical skills.
• Excellent communication and teamwork skills.
  
  

If you are passionate about digital design and verification and have a strong understanding of verification methodologies, we encourage you to apply. This is Onsite role with social media giant.

Skills: digital design,problem-solving,teamwork skills,digital designs,analytical skills,synopsys vcs,communication skills,systemverilog,design,cadence xcelium,uvm,digital,verification methodologies,constrained-random verification methodologies,systemc