Physical Design Engineer

KEY RESPONSIBILITIES

• Lead efforts to translate customer designs into Honeywell’s ASIC technology (RTL to GDSII)
• Execute and address Floor-planning, Power grid design and deployment, achieve timing closure complying to timing constraints, harmonize DFT-insertion needs with physical design needs, configure for and pass physical verification requirements
• Execute design work fully on-site when required (e.g., Classified Designs)
• Present and participate in project phase gate reviews
• Prepare Documentation
• Mentor junior engineers

Tools We Use:

• Synopsys Design Compiler
• Synopsys PrimeTime
• Synopsys DFT Compiler
• Synopsys IC Compiler
• Synopsys TetraMAX
• Siemens Tessent MemoryBIST
• Ansys Redhawk
• Synopsys IC Validator
• Siemens Calibre

YOU MUST HAVE

• Degree in Electrical Engineering or Computer Engineering
• 5 years of ASIC Physical Design experience
• Ability and willingness to work on-site at Plymouth, MN. (zip code 55441)

WE VALUE

• 5 or more years of experience with digital IC design using Synopsys EDA tools
• Strong scripting language skills – e.g., Perl, Shell, TCL, C
• Strong technical problem-solving skills
• Windows OS and LINUX OS and Microsoft office suite tools proficiency
• Effective and clear communication skills and good ability to work with others
• Work accurately with excellent attention to detail
• Ability to work simultaneously on multiple projects and follow up on responsibilities
• Self-starter who requires minimal oversight
• Experience with Siemens Physical Verification tools and methods
• Radiation effects analysis knowledge/experience
• Advanced node and SOI CMOS technology design experience