What are the responsibilities and job description for the Principal Design Verification Engineer - Memory Interface Chips position at Rambus.com?
Overview
Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Principal Design Verification Engineer to join our MIC (Memory Interface Chip) team in San Jose, CA. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer.
As a Principal Design Verification Engineer, you’ll play a pivotal role in MIC product development. In this full-time role, you’ll report directly to our Sr Dir Analog Engineering. Our MIC team is dedicated to developing DIMM Interface Chip, and your contributions will be instrumental in PMIC / TS / SPD projects.
Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.
Responsibilities
- Understand the architecture of the chip and functional blocks.
- Develop / maintain verification environments for chip level verification and enhance / use the automated regression infrastructures.
- Create test plan and develop test cases / sequences in UVM.
- Debug functional issues in the DUT based on the good understanding of the architectural specification.
- Closely work with Design / Architecture / Circuit team to identify and align with the Milestones and Quality metrics of the project.
Qualifications
J-18808-Ljbffr
