What are the responsibilities and job description for the System Verilog UVM Verification position position at Ripple Technology Inc.?
Qualifications :
BS or higher degree in EE, CS or related fields,
Experience requirements :
1 - 5 or more years of direct DV experience
Proficiency in System Verilog Code , Object Oriented Programming, Scripting Languages
Experience in UVM development
Detailed understanding of UVM methodology, flows and test-bench structures
Basic understanding of IEEE802.11 PHY and MAC standard
Experience in debugging designs of IP level (Wi-Fi Baseband, and MAC) or SOC level
Good communication and documentation skills
Responsibilities :
work with RTL designers to do SystemVerilog DV code and UVM DV code, RTL debugging.
Architect and build IP and system UVM verification environments.
Create IP and system verification coverage plans, and generate test cases, based on the specification and review the plan with system architects and design engineers
Report failures, participate in the debugging with various teams, and track bugs
Conduct verification regressions, analyze the results, and review with design teams
Develop verification flows for code coverage and functional coverage for Baseband, MAC, and SOC
Keep a pulse on the job market with advanced job matching technology.
If your compensation planning software is too rigid to deploy winning incentive strategies, it’s time to find an adaptable solution.
Compensation Planning
Enhance your organization's compensation strategy with salary data sets that HR and team managers can use to pay your staff right.
Surveys & Data Sets
What is the career path for a System Verilog UVM Verification position?
Sign up to receive alerts about other jobs on the System Verilog UVM Verification position career path by checking the boxes next to the positions that interest you.
