What are the responsibilities and job description for the Cache Microarchitecture & Logic Design position at Rivos?
Positions are open for full-time in the areas of Cache microarchitecture and logic design.
Responsibilities
As a Cache Microarchitecture & Logic Design Engineer, you will own or participate in the following : Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specificationDevelopment, assessment, and refinement of RTL design to target power, performance, area, and timing goalsDesign delivery - work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and powerValidation - support test bench development and simulation for functional and performance verificationPerformance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performanceRequirements
Thorough knowledge of microprocessor or SOC design with 2 years of direct work experience in one or more of the following areas : High performance cache controllers - pipeline design, hazard detection, parity / ECC generation, coherency policies, replacement policiesCoherent on-chip Fabrics for high performance SOCs and design of associated control structuresKnowledge of SystemVerilogExperience with simulators and waveform debugging toolsKnowledge of logic design principles along with timing and power implicationsUnderstanding of low power microarchitecture techniquesUnderstanding of high performance techniques and trade-offs in a CPU microarchitectureExperience in C or C programming
Education and Experience
PhD, Master's Degree or Bachelor's Degree in technical subject area.
