What are the responsibilities and job description for the FPGA Design Engineer position at RLA Engineering?
Job Title : FPGA Design Engineer
Employee Type : WS
Expected Weekly Hours : 40 (Possibly 5 hours of OT per week)
Location : Redmond, WA 98052 (HYBRID)
Pay Rate : $63.14-$65.37 per hour
Position Summary
This position is responsible for supporting engineers in the client's business unit(s) by providing RTL designs and firmware support for FPGA based emulation of the client's ASIC / SoC IP.
Responsibilities
Understand various FPGA platforms and optimize their environments to yield highly valuable RTL designs for testing
Understand assigned design needs from an ASIC's specification, architectural design, functional models, etc. to optimize RTL synthesis planning
Develop test plans, test benches, and test coverage models to verify and debug RTL code and synthesized netlists
Use various hardware description languages
Utilize design for testability methodologies
Use various synthesis tools
Utilize various programming / scripting languages for test automation
Help develop logical equivalence checking work flows including up to formal equivalence verification
Work on high-end FPGA platforms and collaborate with IC design, pre-silicon verification, and validation engineers across IP blocks
Document issues and propose recommendations to team including senior management
Occasionally work 40 hours in a week to meet certain team milestones
Perform other duties as needed
Education and Credential Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, or related field; Preferred Master's degree
Eligible to work in the US without RLA sponsorship for employment visa status
Experience Requirements
10 years of experience in an FPGA design engineer role
Minimum 5 years of experience with FPGA
Minimum 5 years of experience with Verilog / System Verilog
Minimum 5 years experience with Python or equivalent scripting
Experience converting circuit block diagrams, pseudo code, reference circuit schematics, and other functionality descriptions to RTL using hardware description languages
Experience using FPGA IDEs such as Quartus Prime, Vivado, ISE, or similar tools
Experience using various RTL synthesis tools such as Design Compiler, Fusion Complier, Genus, or similar tools
Experience using equivalence checking tools such as Candence Conformal, Synopsys Formality, or similar tools
Experience debugging RTL and netlists through verification workflows
Experience developing test applications / automation and data analysis reports using programming languages such as TCL, Python, Perl, SQL, UNIX bash / Makefile
Experience working on cross functional teams including analog / digital / mixed signal IC design and layout engineers
Skills Requirements
Ability to read, write, and speak English proficiently
High proficiency using productivity software such as M365 (Word, Outlook, Excel, PowerPoint, Visio, Teams, and SharePoint)
Ability to use project / program management principles and methodologies to consistently meet task deadlines, triage changing priorities, and track issues to resolution
Ability to collaborate across diverse teams with a customer service mindset
Work Environment
The position typically operates in a standard office environment and / or from employee's home
This is a Hybrid position located in Redmond, WA, requiring 2-3 days a week onsite and the rest WFH
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