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Digital IC Design Engineer (RTL, Synthesis, Place & Route)

Saaz Micro Inc.
Camarillo, CA Full Time
POSTED ON 2/19/2025
AVAILABLE BEFORE 8/14/2025

Job Title: Digital IC Design Engineer (RTL, Synthesis, Place & Route)

US Citizenship or US Permanent Residency (green card) required

Hybrid on-site (Camarillo, California) with remote option

Job Description:

Saaz Micro, located in Camarillo, California, is seeking a motivated Digital IC Design Engineer with experience and expertise in RTL design, synthesis, and place & route to join our growing team. As part of the digital design team, you will be responsible for developing and optimizing complex digital integrated circuits (ICs) for a wide range of imaging applications. The ideal candidate will have hands-on experience with RTL coding, synthesis tools, and physical design tools to deliver high-performance, power-efficient, and reliable designs.

Saaz’s advanced R&D in digital electro-optical and infrared (EO/IR) sensors and cameras enables deployment on spacecraft, drones, autonomous vehicles, and smart applications on land. These cameras can detect visible light, infrared, and ultraviolet light—capabilities beyond the reach of standard camera technology


Key Responsibilities:

  • RTL Design: Develop and maintain RTL code (Verilog/VHDL) for complex digital systems, ensuring functionality and performance requirements are met.
  • Synthesis: Perform logic synthesis using industry-standard tools (e.g., Synopsys Design Compiler, Cadence Genus) to convert RTL into gate-level representations, ensuring optimal timing, area, and power.
  • Simulation/Verification: using Xcelium (Cadence), Questa (Mentor/Siemens) or VCS (Synopsys)
  • Place and Route (P&R): Work closely with the physical design team to ensure the successful place and route of digital circuits using tools like Mentor Graphics Aprisa (or others) on meeting timing constraints, optimizing area, and ensuring minimal power consumption.
  • Timing Analysis: Perform static timing analysis and identify bottlenecks in the design. Optimize the design to meet performance and timing constraints using various optimization techniques.
  • Collaboration: Work with cross-functional teams, including verification, physical design, and firmware engineers, to deliver a fully integrated and verified product.
  • Debugging and Analysis: Investigate and resolve issues that arise in the RTL, synthesis, or P&R phases. Provide solutions to fix timing violations, hold time violations, and other critical issues.
  • Documentation: Create detailed documentation for design processes, methodologies, and best practices.

Required Skills & Qualifications:

  • Educational Background: Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • Experience: 0 to 3 years of experience in digital IC design, including RTL design, synthesis, and place & route.
  • Skills in RTL: Proficient in Verilog/VHDL for RTL coding and understanding of digital design concepts (FSM, pipelining, etc.).
  • Synthesis Tools: Expertise in using industry-standard synthesis tools like Synopsys Design Compiler or Cadence Genus.
  • Place and Route Tools: Strong experience with physical design tools such as Cadence Innovus, Synopsys IC Compiler, or Mentor Graphics Calibre.
  • Timing Analysis: Knowledge of static timing analysis (STA) and tools like PrimeTime or Synopsys DSO.
  • Power Optimization: Familiarity with low-power design techniques and tools for optimizing power consumption in digital ICs.
  • Debugging Skills: Strong debugging skills using tools like SignalTap or similar logic analyzers for RTL design verification.
  • Communication: Excellent verbal and written communication skills, with the ability to collaborate effectively across teams.
  • Problem-Solving: Strong analytical and problem-solving skills, with the ability to optimize designs at various stages of the development flow.

Other desired Skills:

  • Experience with 180nm, 90nm, 65nm or advanced process nodes 45nm and below.
  • Familiarity with EDA tools such as Synopsys IC Validator, Mentor Graphics Calibre, or Cadence PVS.
  • Knowledge of DFM (Design for Manufacturability) and DFT (Design for Test).
  • Experience with FPGA prototyping or hardware emulation.

Benefits:

If you are passionate about digital IC design and have the skills and expertise to drive innovation, we would love to hear from you. Apply today and join our team of experts committed to shaping the future of IC design for imaging applications.

Saaz offers a dynamic and innovative work environment, competitive compensation, comprehensive healthcare with dental, and vision plans, retirement 401k option and opportunities for professional growth. Join our team to contribute to cutting-edge semiconductor technologies and make a tangible impact on the future of IC design.


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