What are the responsibilities and job description for the Memory Controller Micro-Architect/Logic Designer (Contractor) position at Samsung Electronics GmbH?

Memory Controller Micro-Architect / Logic Designer (Contractor)

Job Location : 3900 N Capital of Texas Hwy, Austin, TX, USA

3655 N 1st St, San Jose, CA, USA

Post Time : Posted 2 Days Ago

Job # : R97868

Position Summary

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Role and Responsibilities

As a Memory Controller Micro-Architect / Logic Designer, you will be responsible for working on the micro-architecture development of custom memory controller for LPDDR5, LP. In this role you will be interacting with the system architects, verification, performance / power and design implementation teams. You will be owning and driving the critical memory controller related RTL design, performance and power optimization and also work on logic debug and timing closure of the design. Solid engineer foundation and RTL design experience are desired for success.

You drive the timely development and debug of new features on timely development of custom memory controller.
You work on SOC IP delivery with all sanity checks.
You work on timing debug and closure.
You work on LINT, CDC flows and analysis, and ECO flows.
You work on power artist flow and power analysis.
You coordinate with the verification team to verify the functionality and correctness of the design.
You collaborate with implementation teams to achieve your timing and area.
You produce quality RTL on schedule meeting PPA goals.
You engage with performance and power team on achieving performance and power goals.
You partner with the physical design and CAD team to resolve implementation level details.

Skills and Qualifications

10 years of experience with a Bachelor’s degree in Computer Science / Computer Engineering / relevant technical field, or 8 years of experience with a Master’s degree, or 6 years of experience with a PhD.

Strong background owning and driving the RTL design of various sub-blocks of custom memory controller designs.

Demonstrated experience of successful Architectural through RTL design experience on high performance digital designs.

Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis & ECO.

Knowledge of memory controller u-architecture.

Familiarity with different memory technologies like LPDDR4 / 5, HBM.

Knowledge of JEDEC memory standards preferred.

Knowledge of AES, ECC, RAS features preferred.

Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.

Experience with a scripting language like Perl or Python.

Energetic, curiosity, and passion in logic design.

Good written and verbal communication skills.

Our Team

Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. Our team plays a key role in influencing the product roadmap for a market-leading system IP solutions. We focus on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem.

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture.

Total Rewards

The hourly rate range for this role is between $90 and $120 per hour. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

Trade Secrets

By submitting an application, you [applicant] agree[s] not to disclose to Samsung, or induce Samsung to use, any confidential or proprietary information (including trade secrets) belonging to any current or previous employer or other person or entity.

SARC #ACL #Hybrid

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Salary : $90 - $120

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Memory Controller Micro-Architect/Logic Designer (Contractor)

What are the responsibilities and job description for the Memory Controller Micro-Architect/Logic Designer (Contractor) position at Samsung Electronics GmbH?

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