Senior Engineer, DRAM

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We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

What You’ll Do

The DRAM Design Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, NAND Flash.  DDL’s vision is to solve key problems in developing next-generation DRAM solutions, including High Bandwidth Memory (HBM). We are an integral part of Samsung’s strong R&D focus and lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.

Come join the team that is designing HBM product, developing DRAM architecture, co-working head office and managing customer in all stages of design. You’ll focus on enhancement of full chip sim check, DFT consultation, IDD / PDN / checking reliability by developing the architecture of DRAM and optimize it for mass production.

Location: Hybrid with at least 4 days in office in San Jose, CA office location remainder of time to work remotely.

Job ID: 42546

• Develop DRAM architecture and optimize floorplan for next generation DRAM
• Lead design specification, performance analysis and test plan etc.
• Technical interactions with internal and external customers
• Develop ROW, Column Bank architecture design and related test modes
• Develop methods to reduce DRAM power consumption
• Analyze electrical data from Si and validate new core design architecture performance
• Develop and implement a DFT architecture and methodology for the product
• Power delivery network floor planning and optimization
• Collaboratively design with cross-functional teams, such as product managers, engineers, and marketers, to ensure that designs align with the product vision and strategy
• Identify device requirements for the advanced memory product design
• Collaborate with process integration, quality assurance, product engineering and modeling group for DRAM design architecture and technology optimization

What You Bring

• PhD with 0 years of experience in DRAM or related technical field preferred.
• Graduation date between May 2024 - May 2025 required
• Required knowledge, achievements, and skillsets in memory design.
• Proficient with design software and statistical analysis tools.
• Comprehensive understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis
• Expertise in DRAM product development (DDRx, GDDRx, LPDDRx, HBMx, etc.) preferred
• Strong experience in DRAM I/O interfaces and SERDES preferred
• Proficiency in DRAM full chip functional verification preferred
• Demonstrated track record of innovation and creativity in problem solving
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

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When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.

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