What are the responsibilities and job description for the Design Rule Engineer (Creator of design rules) position at SIDRAM TECHNOLOGIES?
Role: Design Rule Engineer (Creator of design rules)
Location- Remote
Must be US citizen
Rate :: Open
Job Description ::
Calculating and writing technology ground rules for semiconductor processing.
Job Duty 2 – Review and Debug manual layout and DRC checking results.
Job Duty 3 – Work closely with Process Integration and Patterning leads to define required technology design rules.
Job Duty 4 – Evaluate and disposition design waivers for testsite macro design.
Job Duty 5 – Aid in development of standards and ground rule automation creation.
Strong Experience with calculating and writing technology groundrules for semiconductor processing including Front End Of Line (e.g., FETs, Resistors, MOSCAPs), Middle Of Line (e.g., Contacts, Local Interconnect), and Back End Of Line (e.g., Inductors, MimCaps, Metal-to-Metal Capacitors), at least 5 years.
Strong understanding of physical layout and leading-edge semiconductor processing, at least 5 years
Experience using the Cadence Virtuoso layout design tool or other EDA layout design tool, at least 5 years.
Preferred: Experience with semiconductor processing
Preferred: Experience with calculating and writing technology groundrules for advanced design nodes (e.g., 5nm, FinFET, Multi Patterned process, DFM).
Preferred: Experience using Synopsys ICV DRC and LVS tool.
Preferred: Experience with Python, other scripting languages, for automation.
Please share resumes to adam@sidramtech.com
Location- Remote
Must be US citizen
Rate :: Open
Job Description ::
Calculating and writing technology ground rules for semiconductor processing.
Job Duty 2 – Review and Debug manual layout and DRC checking results.
Job Duty 3 – Work closely with Process Integration and Patterning leads to define required technology design rules.
Job Duty 4 – Evaluate and disposition design waivers for testsite macro design.
Job Duty 5 – Aid in development of standards and ground rule automation creation.
Strong Experience with calculating and writing technology groundrules for semiconductor processing including Front End Of Line (e.g., FETs, Resistors, MOSCAPs), Middle Of Line (e.g., Contacts, Local Interconnect), and Back End Of Line (e.g., Inductors, MimCaps, Metal-to-Metal Capacitors), at least 5 years.
Strong understanding of physical layout and leading-edge semiconductor processing, at least 5 years
Experience using the Cadence Virtuoso layout design tool or other EDA layout design tool, at least 5 years.
Preferred: Experience with semiconductor processing
Preferred: Experience with calculating and writing technology groundrules for advanced design nodes (e.g., 5nm, FinFET, Multi Patterned process, DFM).
Preferred: Experience using Synopsys ICV DRC and LVS tool.
Preferred: Experience with Python, other scripting languages, for automation.
Please share resumes to adam@sidramtech.com
