What are the responsibilities and job description for the DFT Engineer position at Sintegra Inc.?
**Job Description**
We are seeking a highly skilled Digital Fault Tolerance (DFT) Engineer to join our team.
You will be working with multi-functional teams to implement state-of-the-art designs in test access mechanisms, IO BIST, memory BIST, and scan compression.
Key Responsibilities:
- Collaborate with 3rd party IP vendors to integrate Memory BIST, scan, PHY I/O BIST, and other DFT logic into a streaming scan fabric with a sequential scan compressor/decompressor
- Work with DFT Solutions Vendors to port patterns at the top-level, implement Memory BIST interface in high-performance processor IP, and implement high-speed I/O for the logic scan test
- Collaborate with Physical Designers to validate DFT timing constraints, RTL Designers to verify test design rules, and Test Engineers to bring up patterns on the ATE Automated Test Equipment
- Help develop and deploy DFT methodologies for our next-generation products
**Requirements**
- MSEE or equivalent experience
- 7 years of experience in DFT or related domains
- Solid knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG, and fault simulation
- Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools
- Good exposure to cross-functional areas including RTL & clocks design, STA, place-n-route, and power to ensure making the right trade-offs
- Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development
- Strong programming and scripting skills in Perl, Python, or Tcl desired
**About Our Company**
We are a leading technology company committed to delivering innovative solutions. We foster a collaborative environment that encourages growth and learning.
