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Physical Design Engineer

Sintegra Inc.
Austin, TX Full Time
POSTED ON 4/8/2025
AVAILABLE BEFORE 5/7/2025

Job Description:

We are seeking a skilled Block-Level Design Engineer. The ideal candidate will have experience in RTL-to-GDSII design, including synthesis, floor-planning, place & route, timing/EMIR/PV closure, and signoff.

Key Responsibilities:

  • Perform block-level design from RTL-to-GDSII.
  • Handle synthesis, floor-planning, place & route, timing/EMIR/PV closure, and signoff.
  • Utilize the Cadence Implementation tool suite (Genus, Innovus) proficiently.
  • Implement controllers for High-Speed IO IPs.
  • Conduct structural implementation, including datapaths, bus planning, and routing.
  • Design with multi-power domains.
  • Develop and maintain scripts using TCL and Python.

Requirements:

  • Proficiency with Cadence Implementation tool suite (Genus, Innovus).
  • Experience in structural implementation of datapaths, bus planning, and routing.
  • Strong scripting skills in TCL and Python.
  • Familiarity with multi-power domain design.
  • Experience with controllers for High-Speed IO IPs.

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