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Physical Design Engineer

Sintegra Inc.
Santa Clara, CA Full Time
POSTED ON 1/22/2025
AVAILABLE BEFORE 4/20/2025
  • Block level design from RTL-to-GDSII : synthesis, floor-planning, place & route, timing / EMIR / PV closure, and signoff
  • Proficient with Cadence Implementation tool suite (Genus, Innovus)
  • Structural implementation : datapaths, bus planning and routing
  • Experience with multi-power domain design
  • Solid scripting skills in tcl and python

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