What are the responsibilities and job description for the Device Modeling Principal Engineer position at SkyWater Technology Foundry, Inc.?
This SkyWater Device Modeling Principal Engineer with lead extraction, design, and verification of semiconductor device compact models for new and advanced technologies.
Responsibilities:
New device development, transfer, and integration in a manufacturing environment.
Liaison with Design Enablement group on matters relating device design, and PDK development for CMOS-compatible technologies as needed to support SkyWater foundry technologies.
Device characterization, extraction and validation of Spice-compatible models
Test chip design, layout and characterization as required to support the above technology developments.
Serve as a subject matter expert to customers and SkyWater colleagues for platform technology elements, model constraints, and new device process targeting.
Minimum Qualifications:
MS/PhD Engineering, Physics, or other related field with 6 years related experience.
Expertise in device characterization, extraction, and validation of Spice-compatible models from silicon, using tools such as ICCAP, MBP, and Verilog.
CMOS/MEMS/Photonic device and integration knowledge with relevant combination of years of experience and/or advanced degree.
Comprehensive knowledge of device performance, optimization, and yield limiters relevant to deep-submicron CMOS-compatible technologies.
Expertise in dealing with both internal and external customers.
Clear problem-solving capability, data driven, inventive solution oriented and can articulate thought processes.
Can work both independently and in cross-functional teams for problem solving.
Knowledge of DOE, SPC, and 6-sigma concepts and applications.
US Citizenship Required: This position will require the holding of or ability to obtain government security clearance which requires U.S Citizenship.
Preferred Qualifications:
At least 5 years of advanced device development experience.
Deep understanding of typical IC process design.
Experience in project technology transfers into or out of a semiconductor foundry.
Experience with test chip layout and validation in a Cadence environment.
2-3 years of Project Management skills and/or defined training.
Background in physics-based device simulation, design, and characterization for topics such as PEX, TCAD, noise, ESD mitigation, and stress
Experience in DOE and CMOS device design for extreme environments such as cryogenic, radiation, or high temperature.
