What are the responsibilities and job description for the ASIC Timing Engineer position at Smksoft?
Job Details
Job Title: Chip-Level Timing Constraint Development Engineer
Location: San Jose, CA - You must be already located in the San Jose area.
Duration: 12 Months
Visa: Open (No restrictions)
Responsibilities:
5 years of experience...
Define, develop, and validate timing constraints (SDC) for complex chip-level ASIC designs
Perform static timing analysis (STA) to ensure full timing coverage and closure
Collaborate with RTL, architecture, and physical design teams on clock structures and design intent
Optimize constraints to meet performance, power, and area (PPA) goals
Debug timing issues: clock domain crossings, multi-cycle paths, and false paths
Write and maintain automation scripts using TCL, Perl, and Python
Document timing methodologies and train design teams on best practices
Ensure constraint compatibility with floorplanning, placement, and routing
Salary : $65
