What are the responsibilities and job description for the ASIC Design Verification Engineer (all levels) position at SQL Pager LLC?
ASIC Design Verification Engineer
Client Overview
Our client is building the first latency optimized SoC for their industry. Using its proven AI accelerator designs, we are targeting best in class latency with order of magnitude improvements for years to come.
Low Latency has become the key enabler for their industry and other real-time applications, and the current industry state-of-the-art is just not up to the task. Client has been developing its Neural Net Engines accelerators, optimizing it for Latency and achieving the best LPPA (Latency, Performance, Power, Area) in the field. We are now building the corresponding SoC to deliver unrivaled products to mission-critical and real-time applications.
This is a fast-paced, intellectually challenging position, and you will work with a talented team driven by innovation and excellence. You’ll have relentlessly high standards for yourself and everyone you work with, and you’ll be constantly looking for ways to improve our products' performance, quality, and cost.
We’re changing the meaning of low latency and we want individuals ready to rise up to the challenge and take the industry by storm.
Job Responsibilities
- Architect and build an SoC-level and unit-level UVM verification environment.
- Collaborate with Architecture and Design teams to verify the SoC features according to the chip use scenario.
- Construct the chip level test plans, develop either directed or constrained random test vectors for closing the target coverage.
- Participate in evaluating and selecting third-party VIPs and integrate them into the test bench.
- Debug test failures by collaborating with stakeholders to identify the root cause of the issues.
- Develop and maintain the daily and weekly regressions.
Required Skills
Nice to Have
Education
BSEE / BSCE required
Master in Science preferred.
Featured Benefits
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