What are the responsibilities and job description for the Principal/Senior Staff/Staff GPGPU Design Engineer position at SQL Pager LLC?
Principal / Senior Staff / Staff GPGPU Design Engineer
Client Overview
Client is building the first latency optimized SoC for their industry. Using its proven AI accelerator designs, it is targeting best in class latency with order of magnitude improvements for years to come.
Low Latency has become the key enabler for the niche and other real-time applications, and the current industry state-of-the-art is just not up to the task. Client has been developing its Neural Net Engines accelerators, optimizing it for Latency and achieving the best LPPA (Latency, Performance, Power, Area) in the field. We are now building the corresponding SoC to deliver unrivaled products to mission-critical and real-time applications.
This is a fast-paced, intellectually challenging position, and you will work with a talented team driven by innovation and excellence. You’ll have relentlessly high standards for yourself and everyone you work with, and you’ll be constantly looking for ways to improve our products' performance, quality, and cost.
We’re changing the meaning of low latency and we want individuals ready to rise up to the challenge and take the industry by storm.
Job Responsibilities
- We are seeking a dedicated hands-on GPGPU Design Engineer to help develop a GPGPU for our artificial intelligence computing architecture.
- As a Design Engineer, you will be participating in architecture definition and modeling, verification test plan, and testbench architecture.
- You will be responsible for developing the micro-architecture specification, RTL in Verilog / System Verilog, performance / speed / power goals.
- Collaborate with Algorithm and Verification teams to design various functional IPs in RISC-V based complex SoC.
- Define a micro-architecture for the implementation and the usage of the functional block IP, possibly with externally sourced IPs.
- Participate in SoC level integration and verifications.
- Work with the Physical design team for timing closure.
Required Skills
At least have gone through entire ASIC design phases; from micro-architecture to post-silicon bringing-up and validation.
In-depth knowledge of one of the parallel processing hardware architectures :
Nice to have
Education
BSEE / BSCE or equivalent. Master’s degree in science is preferred, but not required.
Featured benefits
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