What are the responsibilities and job description for the System/FPGA Proto-typing Engineer position at Starcom Consultant?
Position: System/FPGA Proto-typing Engineer
Location: Bay Area, CA (Bay Area onsite as the engineer needs to work in the lab)
Duration: Long-term
Looking for System/FPGA Proto-typing Engineer with strong background in FPGA proto-typing and System design/bringup
Job Description
Sanjay Sharma
E-mail - Sanjay.s@starcomconsultant.com
Starcom Consultant
Skills: fpga,python,prototyping,embedded systems,assembly languages,computer architecture,xilinx fpgas,design,tcl,perl,synopsys haps,unix shells,vivado,board design,typing,makefiles,verilog,siemens profpga,c/c
Location: Bay Area, CA (Bay Area onsite as the engineer needs to work in the lab)
Duration: Long-term
Looking for System/FPGA Proto-typing Engineer with strong background in FPGA proto-typing and System design/bringup
Job Description
- Fluency in Verilog hardware design languages, simulation and debug
- Strong experience with Xilinx FPGAs, Vivado or other FPGA synthesis tools
- Preferred experience with Synopsys HAPS or Siemens proFPGA prototyping flow Experience developing system or IP prototypes using FPGAs
- Software debug experience with C/C and knowledge of low-level assembly languages
- Knowledge of computer architecture and embedded systems
- Working knowledge of board design and debug
- Experience with scripting languages such as Tcl, Perl, Python, Unix shells and Makefiles
- Strong problem-solving skills and methodical work practices
- Ability to with a small close-knit team and own portion or entire proto-typing flow and bringup
- As a Systems engineer you will also be interacting with Architecture, RTL design, and DV teams closely
Sanjay Sharma
E-mail - Sanjay.s@starcomconsultant.com
Starcom Consultant
Skills: fpga,python,prototyping,embedded systems,assembly languages,computer architecture,xilinx fpgas,design,tcl,perl,synopsys haps,unix shells,vivado,board design,typing,makefiles,verilog,siemens profpga,c/c
Salary : $60 - $65
